Generated by Sigasi 2024.2
Revision 2024-10-14
Project dr has 36 design units.
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a real parameter (constant) to a sfp signal by rounding. This module is typically synthesizable, but Cadence Genus might require this tcl command: "set_db hdl_enable_real_support true". Reals that are outside the range of the ufp would throw an $error().
| Name | Type | Default Value | Description |
|---|---|---|---|
float |
real |
0.0 |
input real constant |
| Name | Direction | Type | Description |
|---|---|---|---|
fp |
inout |
sfp.out |
output sfp signal |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a real parameter (constant) to a ufp signal by rounding. This module is typically synthesizable, but Cadence Genus might require this tcl command: "set_db hdl_enable_real_support true". Reals that are outside the range of the ufp would throw an $error().
| Name | Type | Default Value | Description |
|---|---|---|---|
float |
real |
0.0 |
input real constant |
| Name | Direction | Type | Description |
|---|---|---|---|
fp |
inout |
ufp.out |
output ufp signal |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a real input to an sfp signal by rounding. Reals that are outside the range of the sfp would throw an $error(). This module is NOT synthesizable!
| Name | Direction | Type | Description |
|---|---|---|---|
float |
input |
wire real |
input real |
fp |
inout |
sfp.out |
output sfp signal |
unnamed : always_combThis design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a real input to a ufp signal by rounding. Reals that are outside the range of the sfp would throw an $error(). This module is NOT synthesizable!
| Name | Direction | Type | Description |
|---|---|---|---|
float |
input |
wire real |
input real |
fp |
inout |
ufp.out |
output ufp signal |
unnamed : always_combThis design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Addition of sfp signals followed by resizing (equivalant to sfp_add_full + sfp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 + in2) |
u_add_ind :
sfp_add_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Addition of sfp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 + in2) |
in1_aligned : sfpin2_aligned : sfpu_resize_in1 :
sfp_resize
u_resize_in2 :
sfp_resize
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Addition of sfp signals followed by resizing (equivalant to sfp_add_full + sfp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 + in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Multiplication of sfp signals followed by resizing (equivalant to sfp_mult_full + sfp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 * in2) |
u_mult_ind :
sfp_mult_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Multiplication of sfp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = in1.iw + in2.iw and out.qw = in1.qw + in2.qw
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 * in2) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Multiplication of sfp signals followed by resizing (equivalant to sfp_mult_full + sfp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 * in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_resize.sv
This file depends on: fp_if.sv, clip.sv
Change the # of int/frac bits of a sfp signal (without a clipping indicator)
Decreasing # frac bits: truncates LSBs (floor toward -inf)
Increasing # frac bits: pads zero LSBs
Decreasing # int bits: clips or drops MSBs depending on 'clip' parameter
Increasing # int bits: pads zero LSBs (ufp) or sign-extends (sfp)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal |
u_resize_ind :
sfp_resize_ind
This design unit is implemented in fp_resize.sv
This file depends on: fp_if.sv, clip.sv
Change the # of int/frac bits of a sfp signal (with a clipping indicator)
Decreasing # frac bits: truncates LSBs (floor toward -inf)
Increasing # frac bits: pads zero LSBs
Decreasing # int bits: clips or drops MSBs depending on 'clip' parameter
Increasing # int bits: pads zero LSBs (ufp) or sign-extends (sfp)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Subtraction of sfp signals followed by resizing (equivalant to sfp_sub_full + sfp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
u_sub_ind :
sfp_sub_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Subtraction of sfp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
in1_aligned : sfpin2_aligned : sfpu_resize_in1 :
sfp_resize
u_resize_in2 :
sfp_resize
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Subtraction of sfp signals followed by resizing (equivalant to sfp_sub_full + sfp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
sfp.in |
input sfp signal |
in2 |
inout |
sfp.in |
input sfp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a sfp to a resized ufp (without a clipping indicator)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
sfp.in |
input sfp signal |
out |
inout |
ufp.out |
output ufp signal |
u_sfp_to_ufp_ind :
sfp_to_ufp_ind
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a sfp to a ufp: if clip = 1, clips negative numbers then drop the sign sign bit. if clip = 0, simply drops the sign bit. Output must have the same qw and one less iw than the input.
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
sfp.in |
input sfp signal |
out |
inout |
ufp.out |
output ufp signal |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a sfp to a resized ufp (with a clipping indicator)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
sfp.in |
input sfp signal |
out |
inout |
ufp.out |
output ufp signal |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Addition of ufp signals followed by resizing (equivalant to ufp_add_full + ufp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 + in2) |
u_add_ind :
ufp_add_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Addition of ufp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 + in2) |
in1_aligned : ufpin2_aligned : ufpu_resize_in1 :
ufp_resize
u_resize_in2 :
ufp_resize
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Addition of ufp signals followed by resizing (equivalant to ufp_add_full + ufp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 + in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Multiplication of ufp signals followed by resizing (equivalant to ufp_mult_full + ufp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 * in2) |
u_mult_ind :
ufp_mult_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Multiplication of ufp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = in1.iw + in2.iw and out.qw = in1.qw + in2.qw
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 * in2) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Multiplication of ufp signals followed by resizing (equivalant to ufp_mult_full + ufp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal (= in1 * in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_resize.sv
This file depends on: fp_if.sv, clip.sv
Change the # of int/frac bits of a ufp signal (without a clipping indicator)
Decreasing # frac bits: truncates LSBs (floor toward -inf)
Increasing # frac bits: pads zero LSBs
Decreasing # int bits: clips or drops MSBs depending on 'clip' parameter
Increasing # int bits: pads zero LSBs (ufp) or sign-extends (sfp)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
output ufp signal |
u_resize_ind :
ufp_resize_ind
This design unit is implemented in fp_resize.sv
This file depends on: fp_if.sv, clip.sv
Change the # of int/frac bits of a ufp signal (with a clipping indicator)
Decreasing # frac bits: truncates LSBs (floor toward -inf)
Increasing # frac bits: pads zero LSBs
Decreasing # int bits: clips or drops MSBs depending on 'clip' parameter
Increasing # int bits: pads zero LSBs (ufp) or sign-extends (sfp)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
ufp.in |
input ufp signal |
out |
inout |
ufp.out |
input ufp signal |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Subtraction of ufp signals followed by resizing (equivalant to ufp_sub_full + sfp_resize)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
u_sub_ind :
ufp_sub_ind
This design unit is implemented in fp_op_full.sv
This file depends on: fp_resize.sv, fp_if.sv
Subtraction of ufp signals with full precision. Output must have the correct iw/qw for a full width operation: out.iw = max(in1.iw, in2.iw) + 1 and out.qw = max(in1.qw, in2.qw)
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
in1_aligned : ufpin2_aligned : ufpu_resize_in1 :
ufp_resize
u_resize_in2 :
ufp_resize
This design unit is implemented in fp_op.sv
This file depends on: fp_resize.sv, fp_if.sv, fp_op_full.sv
Subtraction of ufp signals followed by resizing (equivalant to ufp_sub_full + sfp_resize_ind)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in1 |
inout |
ufp.in |
input ufp signal |
in2 |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal (= in1 - in2) |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a ufp to a resized sfp (without a clipping indicator)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
0 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal |
u_ufp_to_sfp_ind :
ufp_to_sfp_ind
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a ufp to an sfp by padding a 0 at the MSP as the sign bit. Output must have the same qw and one more iw than the input
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal |
This design unit is implemented in fp_convert.sv
This file depends on: fp_resize.sv, fp_if.sv
Convert a ufp to a resized sfp (with a clipping indicator)
| Name | Type | Default Value | Description |
|---|---|---|---|
clip |
1 |
(if reducing iw) 0 = wrap, 1 = clip |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
inout |
ufp.in |
input ufp signal |
out |
inout |
sfp.out |
output sfp signal |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in clip.sv
Reduce word length of the signed integer input, clipping values higher/lower than the output word length can fit.
| Name | Type | Default Value | Description |
|---|---|---|---|
inw |
0 |
input word length |
|
outw |
0 |
output word length |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
input |
wire signed logic [inw-1:0] |
input |
out |
output |
wire signed logic [outw-1:0] |
clipped output |
clipping |
output |
wire logic |
clipping indicator (active-high) |
This design unit is implemented in clip.sv
Reduce word length of the unsigned integer input, clipping values higher/lower than the output word length can fit.
| Name | Type | Default Value | Description |
|---|---|---|---|
inw |
0 |
input word length |
|
outw |
0 |
output word length |
| Name | Direction | Type | Description |
|---|---|---|---|
in |
input |
wire logic [inw-1:0] |
input |
out |
output |
wire logic [outw-1:0] |
clipped output |
clipping |
output |
wire logic |
clipping indicator (active-high) |